engr_joni_ee
Advanced Member level 3
I guess the typical signal speed on typical FR4 PCB is 15 cm / nanosecond. In 100 picosecond the travelling distance would be:
speed = 15 cm / nanosecond
or 15 cm / 1000 picosecond
or 1.5 cm / 100 picosecond
or 1.5 x 393.7 mil / 100 picosecond
or 590.55 mil / 100 picosecond
590.55 mil in 100 picosecond
I have found the following text from a reference document regarding delay which I guess has direct connection to length matching.
"USB ULPI
PCB and package delay should be kept to 2.0 ns or shorter to meet the 60 MHz operating
target. PCB and package delay skew for DATA[7:0], DIR, NXT, and STP should be less than
±100 ps."
How can I find the length match tolerance in thou from the above info.
speed = 15 cm / nanosecond
or 15 cm / 1000 picosecond
or 1.5 cm / 100 picosecond
or 1.5 x 393.7 mil / 100 picosecond
or 590.55 mil / 100 picosecond
590.55 mil in 100 picosecond
I have found the following text from a reference document regarding delay which I guess has direct connection to length matching.
"USB ULPI
PCB and package delay should be kept to 2.0 ns or shorter to meet the 60 MHz operating
target. PCB and package delay skew for DATA[7:0], DIR, NXT, and STP should be less than
±100 ps."
How can I find the length match tolerance in thou from the above info.
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