Prameeth
Newbie level 4
I am facing an issue with using wire variable of one module in another and have been looking at alternatives. I am writing a verilog code for booth multiplier using fsm (control and data path). In the data path module, I have declared the multiplier register output as wire [15:0] Q. I need to check Q[0] of this register and q-1[a seperate d flip flop] and decided whether to add/subtract or directly shift in the control path module. I can do so in the control path provided I have Q[0] and q-1. Because I declared q-1 as an output port in data path, there is no problem with that however I'm trying to figure out how to use Q[0] variable, which is declared as wire in data path module, inside the control path module. Please help.