Usage of Synchronous and Asynchronuos FIFOs

[Muthuraja.M]

Hi Friends,

I need to know the exact difference Synchronous FIFOs and Asynchronous FIFOs based on its usage and applications.

If the clock frequency is same for EX: read_clk and write_clk is same (10MHz) the write will be fast and read will be slow in that case what type of FIFO need to be used?

If the clock frequency is not same (RD_CLK = 5 MHz, WR_CLK = 10 MHz) the write will be fast and read will be slow in that case what type of FIFO need to be used?

If the clock frequency is not same (RD_CLK = 1 MHz, WR_CLK = 23 MHz) the write will be fast and read will be slow in that case what type of FIFO need to be used?

 

[barry]

It’s not just the clock speed that’s important. Are the clocks SYNCHRONOUS or ASYNCHRONOUS to each other?
Asynchronous FIFOs are more complex.

 

[ads-ee]

Hi Friends,

I need to know the exact difference Synchronous FIFOs and Asynchronous FIFOs based on its usage and applications.

If the clock frequency is same for EX: read_clk and write_clk is same (10MHz) the write will be fast and read will be slow in that case what type of FIFO need to be used?

If the clock frequency is not same (RD_CLK = 5 MHz, WR_CLK = 10 MHz) the write will be fast and read will be slow in that case what type of FIFO need to be used?

If the clock frequency is not same (RD_CLK = 1 MHz, WR_CLK = 23 MHz) the write will be fast and read will be slow in that case what type of FIFO need to be used?

The difference is that asynchronous FIFOs takes clocks that are not synchronous to each other, i.e. they have no phase relationship to each other and can handle transferring data on one clock domain to the other. Synchronous FIFOs must have clocks that are phase locked to each other and need to be an integer multiple of each other, i.e. the lowest frequency clock's rising edge has to always have an edge at the same time as the rising edge of the higher frequency clock.

When the clocks are different frequencies but edge aligned then the transfers are synchronous and the place and route and STA tools can time the setup/hold times between the two clock domains.

On the other hand if you have a 33MHz and a 125MHz clock they definitely should not be considered synchronous even if they are both produced by a single PLL as they are not integer multiples of each other. As they are not integer multiples the rising edges of both clocks will change phase with each other and only align at some beat frequency. Any attempt to perform synchronous transfers between the clock domains will be restricted by the worst case combination of the clocks leading or laging each other and clock tree skew to FFs on different domains. Depending on what the phase relationship between the clock rising edges it might be impossible to meet both setup and hold across PVT. Hence the clocks need to be considered as asynchronous and an async FIFO should be used.

If the clocks are both nominally 100 MHz but produced by two different clock sources then they are asynchronous clocks and the FIFO used is an async FIFO.

What you seem to be asking is instead about throughput of a FIFO with different input output frequencies. This is a fill-drain problem (you can mathematics word problems on this). If you want to have the same data rate going in and out of the FIFO you need a width changing FIFO, which means the FIFO in your second case, 5M(r)/10M(w), you would have a FIFO that has an input that takes two data widths of input and a single data width for output a 2:1 ratio of In/Out. The 1M(r)/23M(w) would have a 23:1 input/output width. All of these FIFOs could be implemented as synchronous FIFOs if the clocks are frequency and phase locked.