Urgent help needed in VHDL

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Ata-Va

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Hi buddy,as Iam new to vhdl I would be very thankful if sb helps me writing a code describing these two lines

where 'Data_In' is a one bit length data and 'Gray_Coded_Data' is std_logic_vector(19 downto 0) and 'i' is integer range 0 to 19;

process( falling_edge(Absolute_Encoders_Clock))

if ( falling_edge(Absolute_Encoders_Clock) ) then

Gray_Coded_Data := ( i => Data_In ,others=>unaffected);

i := i+1;

end if;

actually i thought of shift right logically(srl) but it didn't work much to my surprise

sth like the blove code in matlab

for i=1:1:20
if (falling_edge=1)
Gray_Coded_Data(i)=Data_In ;
i := i+1;
end if;
end;


thx every body
 

Please post the full code you're having problems with - there are all sorts of problems with the VHDL you posted, so post the full code and the errors.
 

And please specify the intended operation. Shift register isn't the same as circularly muxing an input bit. The essentially point is how input and output are synchronized, when should the result be valid?

How about a basic shift register?
Code: 
process (clk)
begin
  if rising_edge(clk) then
    output_data <= input_bit & output_data(19 downto 1);
  end if;
end process;
 

I think there was a miss understanding what I really want is the code below matlab code but I don't know how to translate it in vhdl.

for i=1:1:20
if (falling_edge=1)
Gray_Coded_Data(i)=Data_In ;
i := i+1;
end if;
end;


be aware that data_in changes and is not constant
 

the matlab code is nothing mroe than:

Code: 
process(clk)
begin
  if falling_edge(clk) then
    gray_coded_data <= (others => data_in);
  end if;
end process;
 

i said Data_In is not constant it changes every time like a serial line, I should read serial line and store it in std_logic vector, I think it should be done by sth like code like this

elsif ( falling_edge(Absolute_Encoders_Clock) and (not(Reset)) = '1' ) then

Gray_Coded_Data := ( ( Gray_Coded_Data srl i ) + Data_In ) ;

i := i+1;
but after checking syntax this error massage appears srl can not have such operands in this context.
 

Unfortunately each of your specifications is partly different and also the matlab code doesn't seem to make sense (at least falling_edge = 1). How about showing a timing diagram, a hardware circuit or an exact text description?
 

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