karthiga05
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This is my current 4-bit count up counter. Im still stuck at the portmapping part. would really love ure help! thanks. im not sure whr c_out and cin goes to. im not sure if this is the right method too.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(count
clk:in std_logic;
reset:in std_logic);
end counter;
architecture behav_counter of ha is
component ha port (a: in std_logic;
b: in std_logic;
sum: out std_logic;
c_out: out std_logic);
end component;
component fa port (a, b: in std_logic:='0';
cin:in std_logic;
sum, cout: out std_logic);
end component;
signal a: std_logic_vector(3 downto 0);
signal b: std_logic_vector(3 downto 0);
signal s: std_logic_vector(3 downto 0);
signal cout: std_logic;
--configuration specification
for ha1, ha2: ha use entity work.ha(rtl);
for fa1: fa use entity work.fa(fa_behav);
begin
counter
begin
if reset'event and (reset = '1') then
s <= (others => '0');
elsif clk'event and (clk='1') then
ha1:ha port map(a => a(3), b => b(3), sum => s(3), c_out => cout(3));
ha2:ha port map(a => s(3), b => b(2), sum => s(2), c_out => cout(2));
fa1:fa port map(a => , b => , cin => , sum => ,cout => );
end if;
end process;
count <= s;
end behav_counter;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(count
clk:in std_logic;
reset:in std_logic);
end counter;
architecture behav_counter of ha is
component ha port (a: in std_logic;
b: in std_logic;
sum: out std_logic;
c_out: out std_logic);
end component;
component fa port (a, b: in std_logic:='0';
cin:in std_logic;
sum, cout: out std_logic);
end component;
signal a: std_logic_vector(3 downto 0);
signal b: std_logic_vector(3 downto 0);
signal s: std_logic_vector(3 downto 0);
signal cout: std_logic;
--configuration specification
for ha1, ha2: ha use entity work.ha(rtl);
for fa1: fa use entity work.fa(fa_behav);
begin
counter
begin
if reset'event and (reset = '1') then
s <= (others => '0');
elsif clk'event and (clk='1') then
ha1:ha port map(a => a(3), b => b(3), sum => s(3), c_out => cout(3));
ha2:ha port map(a => s(3), b => b(2), sum => s(2), c_out => cout(2));
fa1:fa port map(a => , b => , cin => , sum => ,cout => );
end if;
end process;
count <= s;
end behav_counter;