Ok, so the DAC and "multiply this signal by a carrier wave" have been removed from the question?
To receive the data in the FPGA you need oversampling. The simplest is integer oversampling and 3 or any higher oversampling factor will work. It is not necessary to get the exact baudrate. The margin depends on the oversampling factor, but 1-2% off is acceptable in most cases.
The basic algorithm is:
1. Wait for the start bit leading edge (the '1' to '0' transition)
2. Wait for half a bit time (this is the main reason for needing oversampling)
3. Check the data bit again, if not '0' it was a false start bit
4. Wait one bit time
5. Sample one data bit
6. Goto step 4 until all data bits have been read
7 Wait one bit time
8 Sample the stop bit, if not '1' it is a framing error
To transmit data from the FPGA to the PC you don't need oversampling