Up/Down Linear Ramp using Op-Amp for timing circuit

Hello,

I am trying to design and simulate a linear ramp generator using an op-amp to be used as part of a timing circuit.

The basic block consists of an integrator. The input voltage is either a 0V or 5V supplied through a micro-controller

When a 5V is supplied to the circuit the output voltage should ramp down linearly until it reaches the ground rail and remains saturated to this rail until the input voltage changes to 0V at which point the output voltage should saturate to the positive rail.

Attached is the circuit and simulation results (using TINA-TI).
View attachment Op-Amp Integrator.bmp
View attachment Op-Amp Integrator Sim Results.bmp

As you may notice in the results, when the input voltage changes there is a delay before the output voltage starts ramping.

I would like to understand where this delay is coming from.
Any insights would be appreciated.

Your cicuit cannot integrate correctly.
Your opamp is operated with a single positive supply. Thus, the output can go positive only.
However, if an inverting integrator sees a positive voltage at its input, it must be able to swing to negative voltages.

Hi,

The problem is obvious when you plot the "- Inp" voltage of the OPAMP.

Usually the voltage is the same as "+ Inp" but you overdrive the input as sopn as the OPAMP output reaches the supply rail....
Some OPAMPs have a problem with this and phase reversal may occur. This means the output goes to the opposite side. Often a disaster..
Avoid this situation.


You run this with a microcontroller. Maybe you can detect "near the rails" and than switch the uCountroller output to HiZ.
A 10k resistor from "+ Inp" back to uController port may improve the "holding" of the value.


Hope this helps

Klaus

As Klaus noted, the op amp no longer can maintain zero relative voltages between the op amp positive and negative input when it reaches the rails but the capacitor keeps charging through R3. That's called "integrator windup". This excess charge must then be removed when the input changes, leading to the delay in the output noted.

The solution is to keep the integrator from saturating, either by detecting the voltage and stopping the integration as Klaus stated, or possibly by placing zeners across the capacitor. The problem with low voltage zeners is that they have a high leakage current and will not limit well with the high integration impedance you have.

Note that the capacitor must be non-polarized (not an electrolytic).

Thank you all for the replies. Now I understand why this is happening.

Unfortunately due to design constraints it is not possible for me to detect a saturation condition. Therefore the only option would be to use Zeners.

Could you please help me understand the limitation due to leakage current you described above?

If you want to keep an integrator swing near to full supply voltage range, zener-clamping isn't an option.

Instead you could try antiparallel schottky diodes across the OP inputs. They limit the wind-up to a small voltage amount and respectively reduce the dead time in integrator output.

Hi FvM could you please clarify the connections?

Thanks,
Michael

- - - Updated - - -

Hi FvM I simulated the circuit with antiparallel shottky diodes across the inputs of the opamp and the circuit works as I wished it would. However I'm not sure I totally understanding the mechanism.

Would you kindly explain to me?

Thanks,
Michael.

Mike@Malta said:

.....................
Unfortunately due to design constraints it is not possible for me to detect a saturation condition. Therefore the only option would be to use Zeners.

Could you please help me understand the limitation due to leakage current you described above?

Click to expand...

At low currents a low voltage zener has a very soft breakdown voltage and will start to conduct µA currents, such as this integrator operates at, well below the stated breakdown voltage. Thus the clamp voltage will be well below the stated zener voltage. You could try experimenting with higher voltage zeners until you find one that gives the desired clamp voltage but that's rather hit and miss.

Below is a simulation of the integrator with a resistor-diode clamp which appears to work well. The relative value of the two resistors determines the clamp level (when the diodes start to conduct) to prevent integrator windup. That may be a preferable way to go.

what is the benefit of connecting V+ to to the +ve terminal of the op-amp?