Unwanted Spikes at the result signal???

Status
Not open for further replies.
M

mohazaga

Full Member level 2
Joined
Aug 18, 2005
Messages
141
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,298
Activity points
2,397
Hi,,,
I hope every body is ok , i have problem of design ckt , well I apply two inverted signal pulse (one delayed to other) to NAND gate .In the result there is some unwanted spikes since the output should be 0 as both signals are 1 (this is ok) but in other cases there are spike ? Why ? how to solve?
thanks
 

i dont know where the spikes appear , you can upload snapshot to clarify , but you may have two kinds of spike:

1- as output is zero except in one combination only, so spikes appear superimposed on the zero level, this cause of the rise & fall time of the two signals, you may notice that this spikes appears on transitions of inputs,and this might not cause a problem ,

2- spikes on while transition from zero to one i.e. the output comes to a higher level than Vdd (or the one level ), this also might not cause a problem as long as the spike value acceptable, it is in this case called overshoot, adding capacitances to the output may eliminate that but will increase your rise and fall time
 

Hi,,,
attached the Input/output waveforms of the NAND for more understanding of the problem, waiting.
thanks



Added after 5 hours 28 minutes:

Hi,,,
the following figure is the real output of the ckt (the outup is taken from NAND gate) where as the input is ideal delayed pulses.
thanks
 

sorry the snapshots too small to see , i cant make them full size , if you can upload larger version , it will be better
 

Hi,,,
when I put noConn terminal on output node the spikes are reduced , what is taht mean?
thanks
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…