Unusual bug in integration VHDL / feedback on component?

-- Discrete integration of n samples

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity time_avg is
	generic(	num_samples: integer := 4;
				auto_configure: std_logic := '1'
				);
	port(	new_data: in std_logic;
			sample: in unsigned(11 downto 0);
			manual_zero: in unsigned(11 downto 0);
			integral: out unsigned(15 downto 0)
			);
end time_avg;

architecture integrate of time_avg is
	
	--type array_type is array(0 to num_samples-1) of unsigned(11 downto 0);
	--signal sample_buffer: array_type;
	signal sum: unsigned (15 downto 0) := X"7FFF";
	signal count: integer := 0;
	signal zero_sampled: std_logic := '0';
	signal zero, first_zero: unsigned(11 downto 0);
	
begin

	process(sample, new_data)
	begin
		-- When new data becomes available..
		if rising_edge(new_data) then
		
			if(zero_sampled = '0') then
				first_zero <= sample;
				zero_sampled <= '1';
			end if;
			
			if(auto_configure = '1') then
				zero <= first_zero;
			else
				zero <= manual_zero;
			end if;
	
			sum <= sum + sample - zero;
			count <= count+1;
			
			if count > num_samples-1 then
				integral <= sum;
				count <= 0;
			end if;
			
		end if;
		
	end process;

end integrate;