Manwe
Newbie level 2
Hi,
I have a piece of Verilog code in an always block (with a posedge clock in the sensitivity list) that I am able to simulate but not synthesize using Synopsys Design Vision:
All statements in the always block are non blocking. Other accesses to the sram module work, and code for those parts can be synthesized. Can someone tell me what's going wrong? Thank you.
I have a piece of Verilog code in an always block (with a posedge clock in the sensitivity list) that I am able to simulate but not synthesize using Synopsys Design Vision:
Code:
ctrlList.sram[addr1] <= 0;All statements in the always block are non blocking. Other accesses to the sram module work, and code for those parts can be synthesized. Can someone tell me what's going wrong? Thank you.