Unsynchronized Crossing Reported by Spyglass CDC in a Sync FIFO

[yuexplore]

Hi,
I met this vio: Ac_unsync02: ... Reason: Gating logic not accepted: only source drive MUX data inputs; at least one destination domain signal should drive a MUX data input. detail schematic is shown in the figure. Any idea about to how to resolve it?

The Aync FIFO I used is from this repo: https://github.com/MahmouodMagdi/Clock-Domain-Crossing-Synchronizers. And I modify these lines in constraints
set_input_delay -clock W_CLK 40 [get_ports R_inc]
set_output_delay -clock R_CLK 8 [get_ports Full]

to

set_input_delay -clock R_CLK 40 [get_ports R_inc]
set_output_delay -clock W_CLK 8 [get_ports Full]

add reset constraints
then do the spyglass CDC.
I attached my .sgdc for your convenience to have a try.

Thank you
Best,
Yue

 

[ThisIsNotSam]

set_input_delay not only sets a number, it tells synthesis whether that input is synchronous to a clock domain. by flipping the commands, you inverted the intended behavior. R_inc is supposed to be linked to the write clock, not the read clock.

 

[yuexplore]

set_input_delay not only sets a number, it tells synthesis whether that input is synchronous to a clock domain. by flipping the commands, you inverted the intended behavior. R_inc is supposed to be linked to the write clock, not the read clock.

How about constraints of FULL? I just don't know why the FULL signal need to be synchronized with R_CLK. In the original constraints, seems all inputs are synchronized with W_CLK and all outputs are synchronized with R_CLK. Could you let me know why we should write constraints like that?