Unsucsessful DRAM loopback operation

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promach

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For this vcd file, why is the DRAM read operation (709746ns) not reading back the DQ values written at the same address (4096) during DRAM write operation (709578ns) ?

Note: read and write latency = five ck cycles



 

The issue seems to have been resolved by incrementing the DRAM address by an amount of BURST_LENGTH instead of just 1
 

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