[SOLVED] unexpected IDENTIFIER error , VHDL

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emmagood

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Hi,

Can anyone tell me the error in the following code:

**********************

entity seven_segment is
Port (rst, clk : in STD_LOGIC;
segment7 : out STD_LOGIC_VECTOR
(7 downto 0);
ca : out STD_LOGIC);

end seven_segment;

architecture Behavioral of seven_segment is

begin

process(rst, clk)

begin

if(rst = '1') then
ca <= '1'; -- for common cathode pin
else(clk'event and clk = '0') --------- error line
segment7 <= "00001100";
ca <= '0';
end if;

end process;

end Behavioral;

************************

the error is : parse error, unexpected IDENTIFIER, expecting AFFECT or EQ or LE

Thanks,
Emma Good
 

Thanks, that helped. I have one more error problem pls.

*************

entity binary_to_7_seg_display is
Port ( binary : in STD_LOGIC_VECTOR (3 downto 0);
seven_seg_output : out STD_LOGIC_VECTOR (7 downto 0);
rst : in STD_LOGIC;
ca : out STD_LOGIC);
end binary_to_7_seg_display;

architecture Behavioral of binary_to_7_seg_display is

begin
ca <='0';

if(rst='1') then ------------------------------ error line
seven_seg_output <= "10000000";

elsif(rst ='0')then

case (binary)
when "0000" => seven_seg_output <= "01111110";
when "0001" => seven_seg_output <= "00001100";
when "0010" => seven_seg_output <= "10110110";
when "0011" => seven_seg_output <= "10011110";
when "0100" => seven_seg_output <= "11001100";
when "0101" => seven_seg_output <= "11011010";
when "0110" => seven_seg_output <= "11111010";
when "0111" => seven_seg_output <= "00001110";
when "1000" => seven_seg_output <= "01111110";
when "1001" => seven_seg_output <= "11001110";
when "1010" => seven_seg_output <= "11101110";
when "1011" => seven_seg_output <= "11111000";
when "1100" => seven_seg_output <= "01110010";
when "1101" => seven_seg_output <= "10111100";
when "1110" => seven_seg_output <= "11101010";
when "1111" => seven_seg_output <= "01100010";

end case;

end if;


end Behavioral;

*************

the error is : parse error, unexpected IF

Thanks,
Emma
 

Code:
entity binary_to_7_seg_display is
Port ( binary : in STD_LOGIC_VECTOR (3 downto 0);
seven_seg_output : out STD_LOGIC_VECTOR (7 downto 0);
rst : in STD_LOGIC;
ca : out STD_LOGIC);
end binary_to_7_seg_display;

architecture Behavioral of binary_to_7_seg_display is

begin

process (rst) is
begin
if(rst='1') then 
seven_seg_output <= "10000000";
ca <='0';
else

case binary is
when "0000" => seven_seg_output <= "01111110";
when "0001" => seven_seg_output <= "00001100";
when "0010" => seven_seg_output <= "10110110";
when "0011" => seven_seg_output <= "10011110";
when "0100" => seven_seg_output <= "11001100";
when "0101" => seven_seg_output <= "11011010";
when "0110" => seven_seg_output <= "11111010";
when "0111" => seven_seg_output <= "00001110";
when "1000" => seven_seg_output <= "01111110";
when "1001" => seven_seg_output <= "11001110";
when "1010" => seven_seg_output <= "11101110";
when "1011" => seven_seg_output <= "11111000";
when "1100" => seven_seg_output <= "01110010";
when "1101" => seven_seg_output <= "10111100";
when "1110" => seven_seg_output <= "11101010";
when "1111" => seven_seg_output <= "01100010";

end case;

end if;

end process;
end Behavioral;
 

You need to include binary in the sensitivity list along with rst, otherwise simulation will likely give erroneous results.

What is up with ca it gets assigned to '0' and nothing else?

Regards
 

Thanks, problem solved. Added process in the program and it is working.

Emma Good.
 

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