kannanunni
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there are many undriven nets in my verilog gate level netlist.
many of the internal wires are UNCONNECTED
is this a problem with RTL code?
this might create any issues in PnR?
please do help...
many of the internal wires are UNCONNECTED
is this a problem with RTL code?
this might create any issues in PnR?
please do help...