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I assume you understand the ratio of Vgs/Vt for Vds with lower Q=CV and reduction of Vt with wavelength of lithographic wafers.

For the fastest CPUs with super low voltage capability, a Vt of 0.2V–0.3V is a reasonable estimate based on current trends.

My Rule of Thumb (RoT) is Vgs/Vt = 2 is nominal Ron and reducing this ratio increases Rds*Cout = Tau while reducing clock rates as Ron = Vdd/Id increases with Vgs=Vds.  While increasing Vdd reduces on and transition time while clocks selected to faster rates it also increases the current during transition which is a linear shoot-thru by design to maintain impedance it does limit the ratio of Vdd Max/Min in all CMOS as this dynamic power to some exponent< ^4?) that I forget.   The original CD4xxx high voltage types which had a Vt= 1.5V and Beta ~= 0.05 had a very high ratio of Vdd max/min.

While traditional Power FETs with Vgs(th) = 2 to 4 V, my RoT is to use 2.5 x Vgs(th) for RdsOn. and lower for the "subthreshold types."