Understanding of Switched Capacitor Amplifier

[taik]

Hi all,

I am trying out a simple SCA setup in simulation to understand the principles of SC.

Below shows 2 pictures of the testbenches I have tried. Which should be the correct one?

I have tried both but unable to get a gain of C1/C2 after running a PSS and PAC analysis in Spectre. I got -50dB gain from PAC plot when my C1/C2=32.

May I know what I should take note of here?

Gain of op-amp is abt 50dB while ideal switches are used from analogLib for the time being.

Thank you.

DC Bias at 1 Input

DC Bias at Both Inputs

Waveform from Circuit 1 for C1/C2=1

 

[jiangxb]

hi taik,

the first plot is right.

you should ensure that CLK1 and CLK2 are the non-overlapped clocks firstly.

just simulate it using transient analysis and check the operating point of opamp and the output.

 

[taik]

i have used non-overlapping clocks for CLK1 and CLK2

 

[yschuang]

I was wondering if the output voltage is right because C1/C2=1. The output voltage is supposed to be 1V when Vin is 0.8 and it is @ 0.8V when Vin is 1V. It turns out this opamp can not go up. That is my another question.

 

[taik]

hi yschuang,

it can still go higher than 0.8V...

but in the first place, is the shape of the output shape correct?

 

[yschuang]

Delta Vin=0.1v and it is an inverting amplifier. Therefore, delta Vout=- delta Vin.
Vout is supposed to be 0.9+delta(Vout), which is 0.9+0.1 when delta(Vin) goes from 0.9 to 0.8. I noticed that Vout goes higher roughly @ 0.975 when Vin is 0.8V.
I will implement an ideal opamp, which is EXXX in Hspice, to compare the result.
Or add an ideal opamp after your own amplifier to get the opposite phase. Doing that you can compare the result with your input.

 

[LvW]

Hi taik, your clock frequency is only (roughly spoken) 5 times higher than the signal frequency. Is this configuration just a test or the final design ? As a rule of thumb, in practice the frequency ratio should be at least 50 !