understanding error voltage link to pll locking status / PID needed

[yefj]

Hello , I have an intresting phenomena when I am trying to lock my PLL by the system shown below.
My error voltage which is IF of a mixer gets amplified and the amplified signal goes into YIG(VCO)
When the phase difference voltage is low and rippling as shown in photo 1, then I see the VCO going crazy back and forth changing the frequency as shown in photo 2.
However when I turn the phase shifter and the error voltage is getting higher then I get straight line error shape and a single tone.
I wonder about two things :
1.When I put big phase shift then IF signal voltage also is high.
High IF signal goes into my amplifier and its getting comppressed (final amount of current going into YIG)
So thats in turn creates a final amount of shift in the VCO so thats why i get a single tone.
But error signal after the feedback is a straight line.
What is the meaning of that?
2. My VCO needs to be connected as negative feedback.
Does it act like the feedback is negative in my system?
Thanks.

 

[yefj]

Hello, I have built a PLL system based on the article attached.
In the scope photos we see the IF signal of the mixer.
When the servo amplifier is ON as shown in photo 3 then the error signal ripple is much much smaller then photo 5.
but the VCO keeps moving decreasing the frequency.
So ripple wise the amplifier is good but the DC shift is not getting fix.
As tony will probably say , show us specs.
my only spec is getting a lock on the resonant frequency of the resonator shown in the diagram below.
We drive the FM coil of the YIG for VCO functionality.
My YIG(VCO) FM coil has the following carachteristics:
sensitivity 400(Khz/mA)
3dB BW 2MHz
resistance 1ohm
inductance 1.5uH
How can I see what kind of PID needed in my situation?
What do you think the PID needs to be to lock in resonant frequency?