I can see what it is supposed to do, my concerns are that the CLK input pin on the 4024 are clearly driven at higher voltages than VDD. It is fed from rectified AC at the input but VDD is dropped to a lower voltage by D2, L2 and R2 and the current through R1, D1 and the ICs. It is using the static protection junctions in the IC to prevent damage. I liken this to driving a car into a wall to stop it instead of applying the brakes, both are effective but one is far riskier than the other.
Q1 base emitter junction is driven by a spike of about 15V as pin 3 of the counter goes high, it has nothing except the junction itself to protect it and it has no leakage to the emitter to fully discharge C4. Again, cost cutting by putting components under stress.
Pin 3 of the 741 is floating to DC, while accepting this is a 50 year old IC and has relatively high input leakage current, it should still be tied to something and protected from overvoltage and to define a default output voltage. A capacitive potential divider is not a good solution to drop the voltage, especially if the PCB substrate is part of a capacitor and subject to environmental effects.
There is also a problem of the whole thing being connected to neutral, this is not a clean signal and connecting the transformer secondary to ground, as is necessary for it to work as a fencer, means the 741 sees not only the spikes from the output but mains borne interference too.
Brian.