Understanding CPPLL stability

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paralinger

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please give me a hand:
Why PLL do not oscillate when open loop gain > 0dB with its phase is around -180 degree in low modulation frequency? How to explain the "phase" of excess phase?Is it periodic?
 

Re: CPPLL stability

paralinger said:
please give me a hand:
Why PLL do not oscillate when open loop gain > 0dB with its phase is around -180 degree in low modulation frequency?
Click to expand...
Look at the closed-loop poles instead! If any closed-loop poles are in the right-half plane the system will be unstable. Open-loop analysis for stability can be confusing unless you apply it correctly.
 

Re: CPPLL stability

paralinger said:
please give me a hand:
Why PLL do not oscillate when open loop gain > 0dB with its phase is around -180 degree in low modulation frequency? How to explain the "phase" of excess phase?Is it periodic?
Click to expand...

I have found this problem too. In Razavi's book<Design of Analog CMOS integrated circuits> Fig 15.36, The low frequency gain is high and phase drift is 180 degree. This may be unstable.
I think the actual low frequency cannot be too low , it is above VCO's lowest working frequency, so low frequency response doesnot need attention.
 

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