Unconstrained PAth in a fulladder design - DC

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Hello everybody,

I'm trying to sinthesize a full combinational design in Design Compiler.

But i'm having some problems with paths unconstrained in report_timing.


Let's start...

Here is an example of .sv code that i'm using to define a fulladder:

Code: 
module fulladder(clk, CIN, A, B, COUT, S);
input logic clk;
input logic CIN, A, B;
output logic COUT, S;
logic fio1, fio2, fio3;

always_ff @ (negedge clk) begin
	fio1 = A ^ B;
	S = fio1 ^ CIN;
	fio2 = A && B;
	fio3 = fio1 && CIN;
	COUT = fio3 || fio2;
end
endmodule

And here is the code that i'm using in Design Compiler to sinthesize it:

Code: 
set verilogout_equation "false"
set verilogout_no_tri "true"
set write_name_nets_same_as_ports "true"
set verilogout_single_bit "false"
set hdlout_internal_busses "true"
set bus_inference_style "\%s\[\%d\]"
set sdfout_no_edge "true"
set fix_multiple_port_nets -all
define_design_lib WORK -path ../WORK

analyze -f sverilog -lib WORK ../RTL/fulladder.sv


elaborate fulladder -lib WORK

create_clock -period 10 -name clk [get_port clk]
set_input_transition -max 2 [get_ports {clk}]
set_input_delay 1 -clock clk [get_ports {CIN A B}]
set_output_delay 1 -clock clk [get_ports {COUT S}]
set_load 0.2 [get_ports {*}]
set_wire_load_model -name 0_5k

link

uniquify
current_design fulladder
compile

change_names -rules verilog -hierarchy

write -format verilog -hier -output ../resultados/fulladder.v
write_sdf -version 2.1 -significant_digits 4 "../resultados/ fulladder.sdf"
write_sdc "../resultados/fulladder.sdc"
report_timing > "../resultados/fulladder_timing.rpt"
report_area > "../resultados/fulladder_area.rpt"
report_power > "../resultados/fulladder_power.rpt"

The report_timing gives me this message:

Code: 
  Startpoint: U6/Q (internal pin)
  Endpoint: COUT (output port clocked by clk)
  Path Group: (none)
  Path Type: max

  Des/Clust/Port     Wire Load Model       Library
  ------------------------------------------------
  fulladder          0_5k                  D_CELLSL_LP3MOS_typ_1_80V_25C

  Point                                    Incr       Path
  -----------------------------------------------------------
  U6/Q (BULX2)                       0.00       0.00 r
  COUT (out)                           0.00       0.00 r
  data arrival time                                  0.00
  -----------------------------------------------------------
  (Path is unconstrained)

Any suggestion about the design and script?
Do you have an explanation about why can't I define the timing path of the project?


Thanks
 

I have not seen adders described like this before.

Why don't you do register the inputs A and B

Code: 
always @(posedge clk)
begin
   A_reg <= A;
   B_reg <= B;
end

then do addition as combinational logic

Code: 
assign {cout,sum} = A_reg + B_reg + cin;

then register the sum output

Code: 
always @(posedge clk)
begin
   sum_reg <= sum;
end


Now if you run DC synthesis tool, it should not report any unconstrained path. The reason is that your adder does not have registered input and output. So even if you specify clock, DC cannot do anything as there are no register.
 

Thanks by your answer.


Indeed, that adder design was a litle bit strange.

I follow your steps, changed the description and tryed to synthesize it again. But the path continues unconstrained. It generates the mapped circuit as before.

What disgust me is that I had synthesized some FIR filters and the tool worked great, so i don't think that is a problem with tool settings.

I tryed to set some load to the inputs and outputs using some D flip flops from technology library, but it doesn't work.
Code: 
set_load [load_of tech_library/D_FLIPFLOP/D_PORT] [get_ports A]
set_load [load_of tech_library/D_FLIPFLOP/D_PORT] [get_ports B]
set_load [load_of tech_library/D_FLIPFLOP/D_PORT] [get_ports CIN]


set_load [load_of tech_library/D_FLIPFLOP/Q_PORT] [get_ports COUT]
set_load [load_of tech_library/D_FLIPFLOP/Q_PORT] [get_ports S]

I'm almost giving up. :/
 

Dude you are complicating the design by adding constraints like set_load etc. On first run do without these.

- - - Updated - - -

Here is what you need

Code: 
module adder_reg
(
input A,B,Cin,clk,rst,
output Cout,
output reg Sum_reg
);

wire Sum;

always @(posedge clk or posedge rst)
  begin
     if(rst)
        Sum_reg <= #1 1'b0;
     else
         Sum_reg <= #1 Sum; 
  end

assign {Cout,Sum} = A + B + Cin;

endmodule

Here is the design compiler script to do the synthesis

Code: 
remove_design -all


set DESIGNS_LIST  {adder_reg}


foreach module $DESIGNS_LIST {
    read_verilog $module.v }

current_design $module
link

# Create user defined variables

set CLK_PORT [get_ports clk]

set CLK_PERIOD 2

create_clock -period $CLK_PERIOD  -name "my_clock" $CLK_PORT
compile

write -format verilog -hierarchy -output $module\_syn.v
write_sdf $module\_syn.sdf


redirect $module.rpt         {report_constraint -all_violators}
redirect -append $module.rpt {report_timing}
report_area -hierarchy    > $module.area
report_cell               > $module.cell
report_hierarchy          > $module.hier
report_net                > $module.net
report_power              > $module.pow
exit

Here is the synthesized netlist
Code: 
module adder_reg ( A, B, Cin, clk, rst, Cout, Sum_reg );
  input A, B, Cin, clk, rst;
  output Cout, Sum_reg;
  wire   Sum, n1, n3, n4, n6, n7;

  DFFSR Sum_reg_reg ( .D(Sum), .CLK(clk), .R(n1), .S(1'b1), .Q(Sum_reg) );
  INVX1 U3 ( .A(rst), .Y(n1) );
  XOR2X1 U6 ( .A(n3), .B(n4), .Y(Sum) );
  OAI21X1 U7 ( .A(n4), .B(n3), .C(n7), .Y(Cout) );
  XNOR2X1 U9 ( .A(A), .B(B), .Y(n4) );
  AND2X1 U10 ( .A(A), .B(B), .Y(n6) );
  INVX1 U11 ( .A(n6), .Y(n7) );
  INVX1 U12 ( .A(Cin), .Y(n3) );
endmodule

Off-course my synthesis library is going to be different from yours but you should be able to synthesize using your library.

Here is the timing report
Code: 
Information: Updating design information... (UID-85)
 
****************************************
Report : constraint
        -all_violators
Design : adder_reg
Version: B-2008.09-SP5
Date   : Wed May 29 17:00:06 2013
****************************************

This design has no violated constraints.

1
 
****************************************
Report : timing
        -path full
        -delay max
        -max_paths 1
Design : adder_reg
Version: B-2008.09-SP5
Date   : Wed May 29 17:00:06 2013
****************************************

Operating Conditions: typical   Library: gscl45nm
Wire Load Model Mode: top

  Startpoint: B (input port)
  Endpoint: Sum_reg_reg
            (rising edge-triggered flip-flop clocked by my_clock)
  Path Group: my_clock
  Path Type: max

  Point                                    Incr       Path
  -----------------------------------------------------------
  clock (input port clock) (rise edge)     0.00       0.00
  input external delay                     0.00       0.00 r
  B (in)                                   0.00       0.00 r
  U9/Y (XNOR2X1)                           0.07       0.07 r
  U6/Y (XOR2X1)                            0.05       0.12 r
  Sum_reg_reg/D (DFFSR)                    0.00       0.12 r
  data arrival time                                   0.12

  clock my_clock (rise edge)               2.00       2.00
  clock network delay (ideal)              0.00       2.00
  Sum_reg_reg/CLK (DFFSR)                  0.00       2.00 r
  library setup time                      -0.08       1.92
  data required time                                  1.92
  -----------------------------------------------------------
  data required time                                  1.92
  data arrival time                                  -0.12
  -----------------------------------------------------------
  slack (MET)                                         1.79
 

Thanks again.

Adder design:

Code: 
module adder_reg
(
input A,B,Cin,clk,rst,
output Cout,
output reg Sum_reg
);

wire Sum;

always @(posedge clk or posedge rst)
  begin
     if(rst)
        Sum_reg <= #1 1'b0;
     else
         Sum_reg <= #1 Sum; 
  end

assign {Cout,Sum} = A + B + Cin;

endmodule

TCL code to design compiler:

Code: 
set search_path {"." "../RTL" "../../XFAB018"}
set symbol_library { D_CELLSL.sdb  }
set target_library { D_CELLSL_LP3MOS_typ_1_80V_25C.db }
set link_library { D_CELLSL_LP3MOS_typ_1_80V_25C.db }
set synthetic_library { dw_foundation.sldb }
set DESIGNS_LIST  {adder_reg}


foreach module $DESIGNS_LIST {
    read_verilog $module.v }

current_design $module
link

# Create user defined variables

set CLK_PORT [get_ports clk]

set CLK_PERIOD 2

create_clock -period $CLK_PERIOD  -name "my_clock" $CLK_PORT
compile

write -format verilog -hierarchy -output $module\_syn.v
write_sdf $module\_syn.sdf


redirect $module.rpt         {report_constraint -all_violators}
redirect -append $module.rpt {report_timing}
report_area -hierarchy    > $module.area
report_cell               > $module.cell
report_hierarchy          > $module.hier
report_net                > $module.net
report_power              > $module.pow

Synthesized netlist:
Code: 
module adder_reg ( A, B, Cin, clk, rst, Cout, Sum_reg );
  input A, B, Cin, clk, rst;
  output Cout, Sum_reg;
  wire   Sum, n1, n2;

  DFRRQLX1 Sum_reg_reg ( .D(Sum), .C(clk), .RN(n1), .Q(Sum_reg) );
  INLX1 U3 ( .A(rst), .Q(n1) );
  EO2LX1 U4 ( .A(A), .B(n2), .Q(Sum) );
  AO22LX1 U5 ( .A(Cin), .B(B), .C(n2), .D(A), .Q(Cout) );
  EO2LX1 U6 ( .A(Cin), .B(B), .Q(n2) );
endmodule



The timing report:
Code: 
****************************************
Report : constraint
        -all_violators
Design : adder_reg
Version: G-2012.06-SP5-1
Date   : Wed May 29 18:34:45 2013
****************************************

This design has no violated constraints.

1
 
****************************************
Report : timing
        -path full
        -delay max
        -max_paths 1
Design : adder_reg
Version: G-2012.06-SP5-1
Date   : Wed May 29 18:34:45 2013
****************************************

Operating Conditions: typ_1_80V_25C   Library: D_CELLSL_LP3MOS_typ_1_80V_25C
Wire Load Model Mode: enclosed

  Startpoint: U5/Q (internal pin)
  Endpoint: Cout (output port)
  Path Group: (none)
  Path Type: max

  Des/Clust/Port     Wire Load Model       Library
  ------------------------------------------------
  adder_reg          0_1k                  D_CELLSL_LP3MOS_typ_1_80V_25C

  Point                                    Incr       Path
  -----------------------------------------------------------
  U5/Q (AO22LX1)                           0.00       0.00 r
  Cout (out)                               0.00       0.00 r
  data arrival time                                   0.00
  -----------------------------------------------------------
  (Path is unconstrained)


1

Could be a problem with the library?
 

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