uncertainty neccessary or not in IC compiler

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asicdesign

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Tight design,reduce uncertainty,It will pasd,so do I need add it during place and rout?
For postlayout STA,do I need add uncertainty?
 
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Uncertainty is a method for:
a. Increasing your ICs margins. Means you close STA timing with better margins which will outcome reliable circuit.
b. As a matter of requirement of your process manufacturer. In most cases vendors will ask you to add uncertainty and will not commit results without it.

Usually the uncertainty is very tight at the start of the flow (placement), than decreases to minimum value at signoff.
Therefore you probably should have uncertainty during postlayout, so you will avoid seeing large slacks during signoff.
 

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