hobbyiclearner
Full Member level 2
Hello there,
I was going through a LCD controller code in VHDL and was unable to understand a particular section
The complete code is in at this link
Basically I am able to understand the entire code except for the above mentioned portion of the FSM (the 'send' state). Particularly, what is meant here by negative enable, positive enable half cycle and negative enable half cycle and most importantly why are these required . Also what is the significance of the particular delay values (1 usec, 14 usec and 27 usec respectively).
Any suggestions here will be gratefully acknowledged.
Thanks,
Hobbyiclearner.
I was going through a LCD controller code in VHDL and was unable to understand a particular section
Code:
...........
WHEN send =>
busy <= '1';
IF(clk_count < (50 * freq)) THEN --do not exit for 50us
busy <= '1';
IF(clk_count < freq) THEN --negative enable
e <= '0';
ELSIF(clk_count < (14 * freq)) THEN --positive enable half-cycle
e <= '1';
ELSIF(clk_count < (27 * freq)) THEN --negative enable half-cycle
e <= '0';
END IF;
clk_count := clk_count + 1;
state <= send;
ELSE
clk_count := 0;
state <= ready;
END IF;
..........
The complete code is in at this link
Basically I am able to understand the entire code except for the above mentioned portion of the FSM (the 'send' state). Particularly, what is meant here by negative enable, positive enable half cycle and negative enable half cycle and most importantly why are these required . Also what is the significance of the particular delay values (1 usec, 14 usec and 27 usec respectively).
Any suggestions here will be gratefully acknowledged.
Thanks,
Hobbyiclearner.