achaleus
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Hello edaboard, I have written one module in Vivado HLS, where simulation waveforms are fine. I generated EDIF from Vivado design suite converted to .NGD using ngdbuild and to verilog using netgen tcl commands from xilinx and done simulation using modelsim. There ap_idle is not getting high even after reset. I stuck here, can you ppl suggest any ideas where I made a mistake. Your reply is much appreciated.
P.S write_verilog from Vivado Design suite generating encrypted .v file giving errors while doing simulation.
P.S write_verilog from Vivado Design suite generating encrypted .v file giving errors while doing simulation.