Unable to Dump VHDL Design Signals in VCD file Using VCS

[Kashif Minhas]

I have got a mixed vhdl & verilog based design with UVM based SVerilog testbench on top. But the waveform only shows SVerilog testbench top & Verilog modules in waveform. VHDL Design files are not added by DVE at all in design hierarchy.

My commands are following:

 

[dpaul]

By any means is it that VCS is showing you only the default waveforms, i.e. only the TB SV signals and the DUT top-level SV signals?
Generally if you do not explicitely add signals the TB signals and top DUT signals will be shown.
But I may be wrong for VCS, had used it years ago!

 

[Kashif Minhas]

Actually, my Design has got VHDL top, other VHDL sub-modules and a verilog sub-module instantiated in it. I try to dump the signals from my UVM based SVerilog TB. But the waveform only shows the TB, instantiated DUT VHDL Top in it and Design verilog sub-module in hierarchy while all the other VHDL design modules are not shown in DUT hierarchy. Could you suggest me why the Design VHDL sub-modules are not showing in design hierarchy in waveform, while they are showing in coverage.

I dump the signals in TB top file through following command:

initial
begin
$dumpfile("dump.vcd");
$dumpvars();
end