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Unable to achieve saturation

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I am a beginner in AC circuit design and im trying to simulate a folded cascode op amp circuit. I manually calculated the W/L ratios for each transistor by assuming V ovp=0.2V and Vovn=0.25V. However, I am facing an issue where not all transistors are operating in the saturation region.

The Vdd is 1.8v.
M1, M2: W/L = 52.77u / 2u = 26.385
M4, M5, M6, M7: W/L = 128.88u / 2u = 64.44
M8, M9, M10, M11: W/L = 57.94u / 2u = 28.97
M3: W/L = 107.4u / 2u = 53.7

I have been trying to resolve this issue for several days and Im apologize if the question is too simple but I’m still unable to achieve saturation even after applying different values for Vbias
.

1737250195384.png
 
Things to try:

* General rule: P type is biased On by applying a voltage closer to ground or negative polarity.
* P type is biased Off by a volt level close to supply voltage.

* Some nodes of your totem poles may provide a volt level (whether a transistor is On or Off) which causes some transistor above or below the node to require a bias voltage which is beyond supply rails.

* Test a mosfet model in an amplifying circuit where it is sole device. Apply a wide range of bias levels while examining performance.

* Use default transistor/mosfet to make a simpler op amp. A long-tail pair is usual. Make one for N-mos and another for P-mos. Get both working.

* Increase your supply rail to say, 9 volts. For years that was a reasonable level for experimenting with.
 
Discard the notion that -every- FET needs to be
in saturation region. It's simply (a) untrue,
(b) impractical, (c) unduly limiting to topology.

Rather, figure where Rout matters and work there.
 
In the shown schematic, output is at Vdd rail. To check transistor bias, you better drive output to mid rail by suitable feedback network. I also wonder what's your input CM spec and how input is currently biased.
--- Updated ---

Increase your supply rail to say, 9 volts
Presume the design objective is low voltage (1.8 V) OP.
 


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