UMC 0.18um erc error

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wang wang

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HI, everyone
I'm using an RNPPO_MM resistor in my circuit. This resistor has three terminals. I've connected the bulk to VDD. In the layout, I folded the resistor and I've used an N_TAP guard ring to surround them, then I've ensured that the resistors' n-well are connected to the guard ring. I've passed DRC and LVS, but I'm encountering some errors in ERC.Please tell me if there is anything wrong with this connection.
 

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k_90 said:
have you checked you pwr/gnd naming in the tool?
Click to expand...
I have confirmed that the issue is most likely not caused by the resistors or power name. The circuit I designed is a bandgap voltage reference, and it seems that the n-well of the BJT in the circuit is causing this error.
 

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wang wang said:
I have confirmed that the issue is most likely not caused by the resistors or power name. The circuit I designed is a bandgap voltage reference, and it seems that the n-well of the BJT in the circuit is causing this error.
Click to expand...
I guess the BJT you used in BGR is PNP, so the NW of the base is connected to VSS. But NW should be connected to VDD generally
so is highlighted by ERC.
Some of the ERC errors are just remind you to confirm the physical connections are what you want and could be waived.
 
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