darcyrandall2004
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uhf mixer
Hello
I am making an attempt at designing a pager receiver. The mixer will consist of a single mosfet.
Attached is the current schematic and the simulated results.
Design decisions I have made include:
1. Mosfet to be operated in the Triode region.
2. IF frequency = 21.4MHz, RF = 454MHZ, LO=475.4MHz
3. Diplexer consisting of High pass and Low pass filter with a crossover frequency
of 1.4*21.4MHz ie 30MHz. The Diplexer presents 50ohm to the mosfet across all frequencies.
4. I am guessing that I need to simultaneously provide an impedance match for maximum power transfer at 21.4MHz, 454MHz and 475.4MHz. This is difficult as the different frequencies require a different load and source impedance for max power transfer. I simply chose 50ohms as the terminating impedance. I measured the input impedance at the two gates of the transistor then provided a conjugate impedance match to the 50 ohm sources, the RF input and LO input.
Attached is the results.
I managed to achieve -5dbm conversion gain. NFssb 56.707
Can anyone make any recommendations as to things I can try or improve on this design?
What sort of performance should I expect to be able to achieve with simple design like this?
Thanks
[/img]
Hello
I am making an attempt at designing a pager receiver. The mixer will consist of a single mosfet.
Attached is the current schematic and the simulated results.
Design decisions I have made include:
1. Mosfet to be operated in the Triode region.
2. IF frequency = 21.4MHz, RF = 454MHZ, LO=475.4MHz
3. Diplexer consisting of High pass and Low pass filter with a crossover frequency
of 1.4*21.4MHz ie 30MHz. The Diplexer presents 50ohm to the mosfet across all frequencies.
4. I am guessing that I need to simultaneously provide an impedance match for maximum power transfer at 21.4MHz, 454MHz and 475.4MHz. This is difficult as the different frequencies require a different load and source impedance for max power transfer. I simply chose 50ohms as the terminating impedance. I measured the input impedance at the two gates of the transistor then provided a conjugate impedance match to the 50 ohm sources, the RF input and LO input.
Attached is the results.
I managed to achieve -5dbm conversion gain. NFssb 56.707
Can anyone make any recommendations as to things I can try or improve on this design?
What sort of performance should I expect to be able to achieve with simple design like this?
Thanks
[/img]