Magnethicc
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Slope compensation is at Pin 11.Is there a slope compensating current coming out of CS pin?...if so, then that will determine the value of the RLF1.
Otherwise, its not RLF1, but its the combination of RLF1 and CLF that matters....as its these two that filter the leading edge spike offf the current sense signal............so basically, you need to use as light current sense filter as possible, so that you dont distort the current sense signal, but not so light that you let through the leading edge spike and other noise.
Also, it depends on your fsw.......higher fsw means lower filtration of this rc.
But you need to scope it and see.......check its filtering off the leading edge spike or not.....
Is this to make the delays more stable?put 330pF to gnd on pins 6,7,8,9 right at the pin, C0G, 0603
people usually use C somewhere between 100pF and 2nF.can you elaborate on what governs the size of R and the size of C? there are infinite combination that will result in the same corner frequency but is there a rule of thumb against too small or too big of a resistor/capacitor?
Why particularly in light load?At 42V 5.5kW ( 135A ) you'll need some pretty impressive film/foil caps across the pir fet H bridge to soak up turn off current - else you'll get volt spikes that'll kill the fets - poof ...
you'll also need some pretty impressive snubbers across Qe, Qf to handle light loads - else poof again ...
oh dear, has your lead designer done anything remotely similar before ... ?I thought at light load Qe Qf are turned on most of the time so no ringing between Xmer leakage and the MOSFET capacitance.
Yeah he has decades of experience with smps design, my comment is based on my knowledge alone, the words are mine not his. I was asking so I could learn as I am a junior in the field.oh dear, has your lead designer done anything remotely similar before ... ?
Thank you cupoftea I will play around with the simulation!Here attached is your 5500W PSFB in the free LTspice simulator.....you can experiment with adding different levels of leakage inductance in the transformer etc...then see how this affects the volts ringing on the output sync rects...i havent added the output sync rects yet, but feel free to do so.....you could even consider the analog part, till your confidence is ok for the ti.com
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Also, please be sure to use SiC FETs......otherwise the PSFB's reverse recovery trick can be played out on you.
I'm with mtwieg. Rather unlikely to see real current ringing with almost montonous voltage waveform.
What's current waveform scale factor, what kind of current probe are you using? What's the boost inverter load case?
Another thing. External parallel diode rarely improves switching behaviour of a poor internal diode.
[quote/] Ok I think I now see what Easy Peasy meant thanks to cupoftea simulation at light load.
Please do correct me if I am wrong - at light load output inductor enters DCM and therefore resonate with the MOSFET output capacitances.
Now my question is why would that ringing cause poof?
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