Between which systems are trying to do this serial communication... Please mention them if possible.
And from which side are you willing to control your communication?
And also mention weather the both side is programmable to you or only single end is in your control?
Actually I am in verification.I need to give input to UART Half duplex present in design for which TX/RX collision is controlled by software.So for that in testbench I have to use one Half duplex UART to give serial input to UARTpresent in RTL.I am having UART model with Full duplex mode..I need to convert into half duplex mode..I am very new to verilog design
my top level pins are
module uart_core (clk,rst,txrx,dir
tx_data,tx_data_valid,tx_data_ack,txd,rx_idle,tx_idle,
rx_data,rx_data_fresh,rxd);
//UART TX instantiation
//UART RX instantiation
input dir;
inout txrx ; //bidir signal
output txd ; //serial output
input rxd ; //serial input
assign txrx = (dir)?txd:1'bz;
assign rxd = dir? 1'bz:txrx;
Is this ok to make it as half duplex? or any other methods are there pls let me know
Thanks
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Could you please provide some material on ISO7816 Complaint UART?
Thanks