ua741cn design
The dual emitter is a real device, of course. You can "model" it in the simplest form by using two transistors with bases and emitters tied together.
Effectively this is a current mirror built into a single "device" at design layout. Doing it as a single device improves the matching which as you know is critical for a good current mirror. Frankly the SPICE models aren't complete enough to know the difference between a merged device like this and two separate devices so it's a decent way to model it.
This is why analog circuit design, physical layout and semiconductor device modeling are such closely allied areas that usually you become an expert in all three when you pick one just one. That doesn't apply so much to digital circuit design though.
Added after 23 minutes:
@snee
The difference between any two manufacturers which isn't *in* the datasheet circuit level diagrams is that the transistors themselves are going to be different: different BF/BR, different IS. different VAF/VAR, etc. You have no way of determining these a priori because those are generally proprietary at least. Further the fab may rev the process and change all of them anyway, which requires that legacy designs will be tweaked by the manufacturer to recreate the datasheet spec values - it is, after all, just a black box product.
As a result the R1 and C5 values will be all over the place based on different manufacturer's individual process design and they may even change over time from the same manufacturer - they are only guaranteeing system level specs so they are free to change the internal implementation any time they want. It only happens that using the same basic topology tends to be the easiest way to change the process without changing the system specs.
The default SPICE BJT parameters will tend to work (they are "reasonable" defaults) but they represent no specific and real manufacturer's BJT process parameters exactly (or sometimes, even approximately).
In terms of military ranges, there are some things you can predict from the topology alone but not everything. Often you have to do process changes to extend operating performance and thus the SPICE model itself would be different. Temperature impact on performance is a big one that is process dependent. Further, reliability of process structures is highly influenced by temperature. Radiation is another one that generally requires specific process changes and knowledge to model.
There are also things that SPICE seriously fails to model well. Variation of parameters is something that every post-Berkeley-SPICE variant has had to bolt-on as an after thought. Most are clumsy and not physics-based in terms of environmental stress to process parameter relationships.
If you are running into student/demo product limits, be aware than pretty much any variant of SPICE will probably work well enough for this kind of simulation. You can use controlled-source macromodels instead of transistor level models but you will loose some specific predictive integrity. Temperature effects is usually the first casualty though not having the actual transistor models isn't much better.
All models are approximations; it's just a matter of what is sufficiently accurate and how much effort is required to attain it.