[SOLVED] uA741 simulation got convergence problem

I got problem in the convergence in bias point calculation during uA741 OP simulation in the PSPICE
And, also study the similar threads to solve this problem like change the parameters like ITL1, ITL4 and others.
But, the problem still can not be solved.
Can someone help me to check the output file data below and tell me how I can solve this problem ? Thanks.

**** 07/05/13 14:57:28 *********** Evaluation PSpice (Nov 1999) **************

** Profile: "SCHEMATIC1-OPtest" [ D:\EE circuit\op001-SCHEMATIC1-OPtest.sim ]


**** CIRCUIT DESCRIPTION


******************************************************************************




** Creating circuit file "op001-SCHEMATIC1-OPtest.sim.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS

*Libraries:
* Local Libraries :
* From [PSPICE NETLIST] section of pspiceev.ini file:
.lib "nom.lib"

*Analysis directives:
.AC DEC 10 1 10Mega
.OPTIONS ITL1= 400
.PROBE
.INC "op001-SCHEMATIC1.net"


**** INCLUDING op001-SCHEMATIC1.net ****
* source OP001
V_V7 VI GND DC 0Vdc AC 50mVac
X_U5 GND N00422 VDD VSS N00436 uA741
R_R4 VI N00422 1k
R_R5 N00422 N00436 1k
V_V4 VDD GND DC 15Vdc AC 0Vac
V_V5 GND VSS DC 15Vdc AC 0Vac

**** RESUMING op001-SCHEMATIC1-OPtest.sim.cir ****
.INC "op001-SCHEMATIC1.als"



**** INCLUDING op001-SCHEMATIC1.als ****
.ALIASES
V_V7 V7(+=VI -=GND )
X_U5 U5(+=GND -=N00422 V+=VDD V-=VSS OUT=N00436 )
R_R4 R4(1=VI 2=N00422 )
R_R5 R5(1=N00422 2=N00436 )
V_V4 V4(+=VDD -=GND )
V_V5 V5(+=GND -=VSS )
_ _(Vi=VI)
_ _(VDD=VDD)
_ _(VSS=VSS)
_ _(GND=GND)
_ _(VI=VI)
_ _(VDD=VDD)
_ _(VSS=VSS)
_ _(GND=GND)
.ENDALIASES

**** RESUMING op001-SCHEMATIC1-OPtest.sim.cir ****
.END

**** 07/05/13 14:57:28 *********** Evaluation PSpice (Nov 1999) **************

** Profile: "SCHEMATIC1-OPtest" [ D:\EE circuit\op001-SCHEMATIC1-OPtest.sim ]


**** Diode MODEL PARAMETERS


******************************************************************************




X_U5.dx
IS 800.000000E-18
RS 1


**** 07/05/13 14:57:28 *********** Evaluation PSpice (Nov 1999) **************

** Profile: "SCHEMATIC1-OPtest" [ D:\EE circuit\op001-SCHEMATIC1-OPtest.sim ]


**** BJT MODEL PARAMETERS


******************************************************************************




X_U5.qx
NPN
IS 800.000000E-18
BF 93.75
NF 1
BR 1
NR 1
CN 2.42
D .87


ERROR -- Convergence problem in bias point calculation


Last node voltages tried were:

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE


( VI) 1.570E+06 ( GND) 1.570E+06 ( VDD) 1.570E+06 ( VSS) 1.570E+06

(N00422) 1.570E+06 (N00436) 1.570E+06 (X_U5.6)-109.3E-06 (X_U5.7) 1.570E+06

(X_U5.8) 1.570E+06 (X_U5.9) 0.0000 (X_U5.10) 1.570E+06

(X_U5.11) 1.570E+06 (X_U5.12) 1.570E+06

(X_U5.13) 1.570E+06 (X_U5.14) 1.570E+06

(X_U5.53) 1.570E+06 (X_U5.54) 1.570E+06

(X_U5.90) 52.79E-06 (X_U5.91) 40.0000

(X_U5.92) -40.0000 (X_U5.99) 1.570E+06


ERROR -- The circuit matrix is too close to being singular to solve.
The diagonal entry for device X_U5.hlim is 9.23E-14 which is too close to 0.
There are two main causes of a singular matrix:
1) A path ending at device X_U5.hlim has a large gain, of the order of 1.08E+13. Or,
2) device X_U5.hlim has a very high impedance to ground, of the order of
1.08E+13 ohms. The readin does a topology check for nodes that
float, but it cannot catch nodes which almost float

Try running with .OPTION STEPGMIN


JOB CONCLUDED

TOTAL JOB TIME .09

The problem is most likely in the schematic which you should post.

Keith

- - - Updated - - -

Also, attach your 741 model as the problem is possibly in there.

Node "GND" isn't connected to SPICE ground node "0". Usual reason is wrong ground symbol in schematic.

I attach a project file

The project file is useless because it doesn't contain a schematic, just meta data. But I don't use Cadence presently and won't check the schematic, may be others will.

There are many similar threads at edaboard, suggesting that PSpice with Orcad schematic entry has some problem for beginners. I suggest to review a working example shipped with PSpice and look at the ground symbols used therein.

Thanks for giving me the answer. and it is solved.
It is very easy to solve this problem as below.
I just replace GND symbol with 0 by editing name in the GND part property.