Dear 2k12,
Thanks for advice
As wp100 and response01 wrote the red colored buffer's enable level on "C" is low, NOT high (see its small circle.... set the PORTD bit 0 as an output. In this case Location "C" in above picture must set to 0 (low) then Z=X by which PORTD bit 0 configure as an output
...
My Question is. the D (Data pin of tris latch ) how gets 0, when BCF TRISD,0 command is executing
please advice
it reads into the internal DATA BUS register (8) the momentary states of the TRISD latches, using a READ TRIS clock pulse for the blue colored buffers (5)
Note the above drawing is not as exact circuit, it shows only the operation principle
Yes, the explanation is perfect, with one exception....operation principle of BCF PORTD,1
Step1.
It reads into the internal DATA BUS register (8) the momentary states of the PORTD pins (NOT the latches !!), using a READ PORT clock pulse for the BLACK colored buffers (Read)
....
SO now X value is zero and x=z from BCF TRISD,1 instruction
In the last questions in my post #16, I asked that (reg being) to replace to FET That mean FET Source = Z(In the above picture ) FET Drain = x and FET G = C
In other words the internal architecture of Tri-State Logic
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