neoflash
Advanced Member level 1
phase margin definition
Rolland Best's PLL book define PLL's phase margin as the phase margin when the loop gain = 0dB.
However, we all remember that when we are design op-amp, we should measure the minimum phase margin when the gain is positive than 0dB. Which way is correct?
Another related question is that type II PLL (PFD + charge pump). There are two poles located at origin "0". Thus the phase shift in low frequency is close to 0degree. How we understand this phenomenon?
Transient response is the final answer. However, I still want to build a bridge between time domain and frequency domain in this topic.
thanks
Rolland Best's PLL book define PLL's phase margin as the phase margin when the loop gain = 0dB.
However, we all remember that when we are design op-amp, we should measure the minimum phase margin when the gain is positive than 0dB. Which way is correct?
Another related question is that type II PLL (PFD + charge pump). There are two poles located at origin "0". Thus the phase shift in low frequency is close to 0degree. How we understand this phenomenon?
Transient response is the final answer. However, I still want to build a bridge between time domain and frequency domain in this topic.
thanks