type constructs in vhdl is corresponding what in verilog

[taoshen]

type constructs in vhdl is corresponding what in verilog?

wire in verilog is corresponding what in vhdl ?

 

[xtally]

type in VHDL is enumeration I guess.. there is no equivalent in verilog.. however you can use "parameter" for decalring states which can be used for the same purpose in VHDl..

corresponding to wire.. you can use "signal"
but reg in verilog can also be a signal in VHDL