two synthesis runs with two separate libraries - different slack numbers

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I have two synthesis run of the same design but with two different libraries. I get two different numbers [both negative slack :-(

Question is the library that is expected to be much faster has higher negative slack time.
Everything else between the two run is identical

What is the best way to debug this.

Thanks,
BIO
 

write a rtl code which as all basic gates and flops, synthesis the code in difference frequency.
This will give idea about which library is better interms tool, performace..

Aravind R
 

aravind said:
write a rtl code which as all basic gates and flops, synthesis the code in difference frequency.
This will give idea about which library is better interms tool, performace..

Aravind R
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Hi Aravind,

This is a 240k gates design. We want to keep all the rtl intact so that we can focus on library. It does involve library of 1000 types cells so it is not easy to do that.
I just wanted to see if there are any dc commands that allows me to dig into the library portion of the design and see how synthesis picked such cells and why what is expected did not turn out to be the faster library
 

For quick understanding about the librarys. Do technology translation on DC. This will give some rough idea bought other library.
U need to do vice-versa

aravind
 

Hi

Run with faster library has worst slack. I wonder how this is possible, I hope the context is about setup time and not hold time, if it is hold then we can expect worst -ve slack for faster library .
In case if it is setup slack, i would like to know if WNS path in both the cases is same.

Br
Sing
 

the netlists synthesised which you used different library may be different. When you use the faster library to synthesis, some path maybe have bigger slave than the slow one, but the total slace may be better than another. If you modify the some of the path to make them have no violation, then the bigger violation path you metioned maybe get better.
 

Hi Aravind,
I am not familiar with technology translation on DC, could you elaborate a little further on how to do it?
Thanks,
Bio

---------- Post added at 14:02 ---------- Previous post was at 14:00 ----------

Hi Sing,
The supposedly faster library has, let us say a WNS of -515ps while supposedly slower library has -320ps. total cell count, total combinational cells, total sequentials, are "almost" identical.

---------- Post added at 14:04 ---------- Previous post was at 14:02 ----------

Hi, I am not sure whether this is the suggestion you made. I realize in synthesis, tool takes different approaches to analyze the design and come up with cell and its usage but my question is, in general , something should be totally broken if a "faster" library has more negative WNS. I am seeking ways to debug it. if you have suggestion, I would take them heartedly.
 

why dont know search DC technology translation in solvnet or DC document. u will a find the command and flow.

Best of luck
 

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