analogengineerrf
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Hello all.
Plz tell me, if it is possible to get a successful Op Amp IC based on 2 stage architecture.
What I see is that, during the Monte Carlo simulation, the gain is varying very huge, and even to the negative gain (-30db), while during the process corner simulation, everything seems to be fine.
The 2nd stage is a common source stage, where I find the gm and gds of the input transistor varying linearly with its width changing.
I am using HSPICE simulator
Thanks in advance.
Plz tell me, if it is possible to get a successful Op Amp IC based on 2 stage architecture.
What I see is that, during the Monte Carlo simulation, the gain is varying very huge, and even to the negative gain (-30db), while during the process corner simulation, everything seems to be fine.
The 2nd stage is a common source stage, where I find the gm and gds of the input transistor varying linearly with its width changing.
I am using HSPICE simulator
Thanks in advance.