two read a text file in vhdl

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
library std;
use std.textio.all;
 
use IEEE.std_logic_unsigned.all;
use std.textio;
 
entity rr is
Port ( address : in  integer;
           dataout : out  integer);
end rr;
 
 
 
   
architecture Behavioral of rr is
 
file data_in : text is in "E:/sample.txt";
type data_array is array(1 to 256,1 to 256)of std_logic_vector(7 downto 0);
signal data1 :data_array ;
 
 
begin 
process
 
type Y_array is array (1 to 256,1 to 256) of integer;
type un_array is array (1 to 256,1 to 256) of unsigned(7 downto 0);
variable Y : Y_array;
variable Y_un : un_array;
variable inline : line; 
variable v_char: character;
begin
for i in 1 to 256 loop 
  assert not endfile (data_in) report "Premature end of file" severity failure;
  readline(data_in,inline); 
  for j in 1 to 256 loop
      read(inline,Y(i,j));
      read(inline,v_char); -- to consume a space character if required
Y_un(i,j) := to_unsigned(Y(i,j),8);
data1(i,j) <= std_logic_vector(Y_un(i,j)); 
end loop;
 
end loop;
wait for 2 ns;
end process;
 
end Behavioral;