Two questions about HDL designer - simulation and attributes

[nettek]

Hi,

I have a large design in HDL designer that includes a graphical state machine block and many other blocks. In the design are also lots of internal signals. There are two things I want to do:

1. Use attributes to preserve the current_state and next_state (or just one of them) signals so I can later view them with SignalTap.
2. Be able to use those internal signals in my testbench for the purpose of simulation. For example, if current_state = X then... I also need to use the other signals in my design, not just state machine signals.

I've seen a potential solution here:
https://stackoverflow.com/questions...rnal-signals-to-testbench-in-vhdl-97-and-isim

But while I did succeed in creating a package, I did not succeed in doing step 2. This is because I don't know how to take a signal that exists in a graphical interface and assign it to a global signal in a package.

So, do you have any ideas? Or, can you help me implement the above solution in HDL designer?

Thank you!

 

[ads-ee]

I'm assuming you can create your own blocks in HDL Designer.

How about trying instead making step 2 be:
Step 2: create a entity with an input port with the signal you are trying to spy. Do the same assignment to the global signal in the architecture. Now you should be able to instantiate this new entity/architecture in your graphical design and hook up that port of the spy block to the signal you want to see in the TB.

I have no idea if this will work or not as I've never used HDL Designer before, but this is what I would try if I was using it.

 

[nettek]

Thank you for your answer, but I've read it multiple times and I don't know how to do what you're suggesting.
Remember it all has to be done graphically, which is what makes it harder.

I was really hoping there is some integrated solution by Mentor graphics themselves for this problem.

I can also just connect each signal I want to spy on to a port but I don't want to constantly add/remove ports, this doesn't feel right...

 

[TrickyDicky]

HDL designer is just a wrapper around existing HDL. All simulations are done in HDL. So you should be able to modify a block that examines a signal anywhere in the design using external names.

 

[nettek]

Lets forget about question 2 for now, as I have somewhat succeeded with simulation in other ways, even though they were somewhat workarounds and not what I wanted.

Question 1 - does anyone know? This is really important to me as I am almost going to test my design in SignalTap and it's imperative I see the state of the state machine in it.

 

[ads-ee]

Add signal tap after the design is implemented (i.e. synth+par) The flip-flops for the FSM will exist in the routed design.

Either that or instantiate the Signal Tap (assuming Intel/Quartus allows this).

 

[nettek]

Add signal tap after the design is implemented (i.e. synth+par) The flip-flops for the FSM will exist in the routed design.

I forgot to add a few details to my post:
1. I have already began testing with SignalTap, just a different, earlier version of the design (since it was made by someone else, I wanted to "get a sense of it").
2. I am synthesizing with Precision. It is "throwing away" many signals it deems unnecessary, like the state machine signals current_state and next_state, and many more that I want to monitor.

That's how I know there are problems with those signals.

Either that or instantiate the Signal Tap (assuming Intel/Quartus allows this).

Can you explain what you mean by that?

 

[ads-ee]

I forgot to add a few details to my post:
1. I have already began testing with SignalTap, just a different, earlier version of the design (since it was made by someone else, I wanted to "get a sense of it").
2. I am synthesizing with Precision. It is "throwing away" many signals it deems unnecessary, like the state machine signals current_state and next_state, and many more that I want to monitor.

That's how I know there are problems with those signals.

To me you should be concentrating on the synthesis warnings and determine why the FSM current_state (flip-flops) are getting removed. Registers should never be removed unless they reduce to a constant, which will result in pruning of the register. Have you gone over every warning/note in the synthesis logs and verified they can be ignored?

Can you explain what you mean by that?

I know Xilinx allows you to instantiate the Chipscope cores directly into a design. Last time I used Quartus 10+ years ago they allowed something similar, but I have no clue if that is something still available in the tools or not.