Two Icons for ChipScope in one Project?

Hello,

I have a design with multiple levels of modules, so when ever I want to check some module outputs on ChipScope I have to bring all those signals all the way to the top level Or the control signal from the Icon on the toplevel down to the module I want to observe the output. So, I am wondering If it is possible to use two or possibly multiple Icons(in different modules so that it will lessen the effort of mapping signals up and down)or a better way of doing this.

I already know that Icon ideally is one and will contain all the ILAs in the toplevel.

Thanks!

You can if you instantiate them in your code. I don't recall what the limit was on how many icon modules you could add in one design. I've only used 2, different clock domains with cross connected triggers.

Regards

I have not used multiple ICONs till now since I thought only i ICON and multiple ILAs.
But since you raised this question I could see some sort of solution which might help you:

http://forums.xilinx.com/t5/Design-Tools-Others/Chipscope-Combine-CORE-INSERTER-with-CORE-GENERATOR/td-p/209081

Like ads-ee said, you can use multiple ICONs. But you had better instantiate them yourself. As far as I'm concerned that advice also applies even if you even if you have only one ICON. Sometimes the xilinx tools muck up the automatic connection for strange reasons known only to Xilinx. Safest & easiest way I found to be to just instantiate them.

Besides what mrfibble mentioned, it's easy to add and `ifdef or the equivalent if statements around the ICON/ILA to selectively compile them into the code or not. I've used this method many times for when I needed to capture some data from the hardware to see what the design was receiving as input data.

Thank you, all comments were helpful! But here comes another problem, the module where I instantiate the second ICON is instantiated multiple times in the whole design. This creates a mapping problem of:

The error makes sense for me, as I am instantiating the same copy of Chipscope core multiple times. Is there a way to solve this rather than moving the core to the nearest toplevel?

Add a parameter/generic to selectively instantiate the ICON or not in that module. Also pass the JTAG_CHAIN attribute for the ICON as a parameter/generic.

Regards

I kinda understand what you mean but what can be used as a generic for an ICON, I mean it is auto-generated by the Core generator right, and somehow the instantiation should match the generated code? Please type me some fragment of code of what you meant. Where can I get the JTAG_CHAIN attribute, or you mean the values 1,2..?

Okay it wasn't an attribute. It's the selection of which CSET user_scan_chain=USER1

So the limit is 4 ICONs in a design as USER1-USER4 are the only options.

Regards

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You know if you are using a 7 series, Zynq, or Ultrascale part you could use Vivado and avoid having an ICON altogether. With Vivado you can just instantiate the ILAs all over the design and the tools add the ICON in. At least that's what the documentation says...Haven't tried it yet.

Regards

Once I changed the ICON parameter to USER2 for the second ICON, it worked fine. The Vivado stuff sounds interesting, I just tried to see how it is done for Planhead but seems to need a bit of a time. Would love to hear from you after you tried it. Thanks!

If you're using one of the later versions of ISE 14.x series then the front end is already "Planahead". The options of making it the GUI look more Planahead like or ISE like is pretty much only cosmetic to present information according to the current usage of the tool, like for partitioning the design, choosing I/O etc.

Truth be told I wish they would have made Vivado support the 6 series parts. I really like the single executable model, the reduced memory footprint, the 3 dimensional placement/router, and the fact you can actual perform all the commands via a Tcl script that keeps the entire design in memory without having to wait for huge files to load for every single command. You can spit out checkpoints, which you can later load leaving you at the precise point you were when you wrote the checkpoint out. You don't even have to open the GUI if you don't want to, but if you do it's just a Tcl command away.

ads-ee said:

Truth be told I wish they would have made Vivado support the 6 series parts.

Click to expand...

Would be awesome, I am also working on 6 series.

You can spit out checkpoints, which you can later load leaving you at the precise point you were when you wrote the checkpoint out.

Click to expand...

This is a life saver man.

ads-ee, the implementation worked fine without any error but when I tried it on chipscope I can't see the second ICON. But I have the following warning, may be it is due to that.
And do I need another ucf file for the second ICON?

PS: Do I have to switch between USER1 and USER2 in the chipscope to see the two ICONS or will all the ILAs and the two ICONS will be shown on one run of the chipscope?

I suspect you may have to use 1 icon If you want to see both at the same time. You only need to pass the control bus through module/entity ports.

Sorry about steering you down the wrong path it's been over a year since I last used chipscope with multiple ILAs.

Thank you for replying, I have already changed it one ICON. You don't have to worry about it, it was interesting to try new things.