What are you wanting to protect?
1) OVP on each supply from line surges?
- Then apply TVS or MOV direct to each PS at source with polyfuse in series.
2) OVP on signals on cables from EMI transients to prevent CMOS latchup? e.g. ESD
- then apply TVS to signal and signal ground close to cable input.
3) ESD ground shift causing CMOS latchup?
Where/how is earth , IO cables and PCB ground connected to case? or is it isolated? ESD transients can be capacitively coupled and CM chokes on cables can attenuate 10ns pulses.
Please see the diagram below
The board contains a 24V logic block made of optocouplers. No CMOS, nor digital stuff.
It has some isolated IO (this is what I want to protect), connected to some remote switches through long cables. These cables are shielded and the shields will connect to cabinet chassis.
The shields connection to chassis must be done at the enter point of the cable to the cabinet, am I right?
I am trying to distribute and route IO and logic elements in a way which allows to have a whole section in one side of the board and the other section in the opposite side, so I can treat them as two separated boards, with solid power and GND planes. Both GND planes will join at power input.
But I do not know if it is a good practice to add a chassis ground to the board too and tie the TVS's to it.
The PCB will be connected to chassis using a wire connected to one of the mounting holes (close to power input).
Some of the TVS's are placed at the opposite corner of the point where the chassis wire will be connected. So, if I tie them to IO GND and an ESD happens, the current will go through the entire board to reach the chassis and earth, am I right?
Thanks
Jose