TTL turn-off delay reduction

[Davood Amerion]

Hi to all;
Who know the detailed description of the 74S00 internal circuit?
I want to know, how R3-R4-Q3 reduce turn-off delay time of Q6.
anybody can explain it?

Thanks in advance.
Davood Amerion

 

[Davood Amerion]

i'm still waiting :?:

 

[echo47]

S and LS gates are similar, so see page 12 of the ON Semiconductor LS TTL Data book:
https://www.onsemi.com/pub/Collateral/DL121-D.PDF

I changed the text's transistor numbers to match your diagram:
Referring to Figure 1, the base of the pull-down output transistor Q6 is returned to ground through Q3 and a pair of resistors instead of through a simple resistor. This arrangement is called a squaring network since it squares up the transfer characteristics (Figure 5) by preventing conduction in the phase splitter Q2 until the input voltage rises high enough to allow Q2 to supply base current to Q6. The squaring network also improves the propagation delay by providing a low resistance path to discharge capacitance at the base of Q6 during turn-off.

 

[Davood Amerion]

Thanks dear echo47;
I understand its role for modifying transfer characteristics.
but what about turn-off delay?
I read in TI TTL Databook [volume2] that this circuit reduce turn-off time Q6.
when we ignore it's role about modifying transfer characteristics,
and compare it's effect for reduction of turn-off delay time,
which one is better, simple resistor or this circuit?

i think, one simple resistor is better.
because it clamp Q6-base to ground.
but in this config. as Vbe going below 0.6-0.7 both of transistor going to off state.
Am i right?