When the TTL output is high, its output transistors are not trying to pull current into the output pin from the positive side of the power supply. As far as the pull-up resistor is concerned, its lower terminal is connected to an approximately open circuit. Therefore, since practically no current flows through the resistor, there's no voltage drop and the lower terminal of the resistor is at the same voltage as the top, which is Vdd.
then what would happen if the output of ttl gate is low ? (transistor of the ttl gate would sink current the same case would happen as you said the current through the resistor would be minimum and hence output would still remain Vdd)
No. When the output transistors sink current in the low state, it means that current is flowing into the output through the resistor. This causes a voltage drop and the TTL output drops to a level as low as is allowed by the output transistor's characteristics.
This may be what's confusing you: If the resistor - the side that's not connected to the TTL output - were connected to ground, then the situation will be reversed. The TTL output will be pulled down to 0V when it is in the low state. In that case, the resistor will be a pull-down resistor.
If it sinks current would the value of the current be large enough for large drop on the pull up resistor thus potential between CMOS gate would be 0(wrt to ground). am i right?
When the TTL output is high, its output transistors are not trying to pull current into the output pin from the positive side of the power supply. As far as the pull-up resistor is concerned, its lower terminal is connected to an approximately open circuit.
That's not entirely true as that would mean a TTL output without anything connected would just sit at whatever voltage it was sitting at before (like near 0V if it was pulled low before).
Let's suffice with saying that TTL outputs are much better at pulling an output low, but rather weak at pulling an output high. And when going high, usually don't go up to the +5V rail, more likely around 3.5-4V. Hence the asymmetric I/O voltage characteristics, preference for active-low rather than active-high control signals, and the (strong!) preference for using pull-up rather than pull-down resistors with TTL logic.
Pull-up with regular push-pull ouputs isn't a specified operation in TTL datasheets, as far as I'm aware of. According to the internal TTL and LSTTL ouput stage configuration, the resistor will pull-up the output level up to Vcc, similar to an open collector output. The rising edge speed for the last third is however slow. Low level shouldn't be a problem with reasonable resistor values.
For fast speed, a TTL compatible 74HCT CMOS input is the better alternative, also saving power losses of pull-up resistors.
The TTL output is a Darlington NPN and runs out of drive about
VCC-1.4V. This puts you well into the linear band of the CMOS
front end and would result in excess shoot-through current (at
best). The pullup settles the TTL output to the rail after the
high side of the totem pole has cut out.
That's not entirely true as that would mean a TTL output without anything connected would just sit at whatever voltage it was sitting at before (like near 0V if it was pulled low before).
That's why I qualified the statement with "As far as the pull-up resistor is concerned" which was meant to indicate that the output does not necessarily behave like an open circuit in all respects. And we were talking only about the high state then.