zelia
Newbie level 1
tspice simulation
i have a problem to measure the phase noise of 4 stage fully differential cmos ring vco.i mean that how can i use the tspice (w-edit) to show the simulation of ring vco phase noise. How can i generate it? how about the kvco gain?can it be generate too?.....
i have done the layout for my ring vco but i didnt do the capasitor layout...after done the lvs..my circuit are equal but when i run the ledit file (layout.spc) using tspice and w.edit.unfortunately, i cant get the same centre frequency eventhough the w n l are equal..and i have put the capaitors command too inside the layout.sp file inorder to simulate it in the tspice. As i had mentioned, i managed to get the correct waveform but not at the same frequency. hope u can reply asap. Thanks 4 the consideration.
i have a problem to measure the phase noise of 4 stage fully differential cmos ring vco.i mean that how can i use the tspice (w-edit) to show the simulation of ring vco phase noise. How can i generate it? how about the kvco gain?can it be generate too?.....
i have done the layout for my ring vco but i didnt do the capasitor layout...after done the lvs..my circuit are equal but when i run the ledit file (layout.spc) using tspice and w.edit.unfortunately, i cant get the same centre frequency eventhough the w n l are equal..and i have put the capaitors command too inside the layout.sp file inorder to simulate it in the tspice. As i had mentioned, i managed to get the correct waveform but not at the same frequency. hope u can reply asap. Thanks 4 the consideration.