Engineer4ever
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Hi,
I am designing a Serializer and the last stage requires a high-speed architecture so I used TSPC topology for flip-flops and latches. The problem is I need the TSPC latch to delay its input signal by half a period and I tried everything but the delay is still about quarter a period. Is there any solution for that problem or is it common that TSPC latch works like that?
Thanks in advance,
I am designing a Serializer and the last stage requires a high-speed architecture so I used TSPC topology for flip-flops and latches. The problem is I need the TSPC latch to delay its input signal by half a period and I tried everything but the delay is still about quarter a period. Is there any solution for that problem or is it common that TSPC latch works like that?
Thanks in advance,