TSPC D Flip Flop Clock not working in cadence virtuoso

[Beaver234]

I was trying to simulate 5T tspc d flipflop in cadence virtuoso(Schematic design), and clock is not working.

Here is the SchematicI have copied the schematic from a research paper).

Clock is give to the gate of NM0 but I have grounded it to see if clock works.

Waveform:
The Output is shown irrespective of clock.
Pls help.

 

[dick_freebird]

So you hooked it up wrong, and it doesn't work, and you
want us to do something... ?

I think this looks like a dynamic DFF and even if hooked
up right, there can be a minimum operating frequency
and 20us (50kHz) may be below that.

 

[Beaver234]

So you hooked it up wrong, and it doesn't work, and you
want us to do something... ?

I think this looks like a dynamic DFF and even if hooked
up right, there can be a minimum operating frequency
and 20us (50kHz) may be below that.

I tried 10u,20u to 60us. It just does not work. I also tried the same circuit in LT Spice and the same problem occured. I really don't know what's going wrong.