TSMC65nm DRC error after sealring

snang

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Hello, I encountered the following error between the seal ring and the pad while designing a chip. Do you happen to know how to resolve this issue?"

 

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It looks like your sealring is too close to the pads. It would be better if you could enable dimming while highlighting the error, so it is more visible. Did you generate your dummies with the sealring, or you added it after?
 

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It looks like your sealring is too close to the pads. It would be better if you could enable dimming while highlighting the error, so it is more visible. Did you generate your dummies with the sealring, or you added it after?
I generate dummies after the sealring. My pad and sealring is attatched now.
 

This is how to enable dimming: Press E for Display settings and enable dimming. After that, select error in Calibre and you will see clearly where it is happening.
As I said in a previous post, your pads are too close to the seal ring. Make a bit of spacing, regenerate dummies and see if the error is gone. Also, you can search for this error in TSMC documentation (Design Rules Manual or something like this)
 
Thank you for your advice. I detach pad with sealring. so, AP.S.4 error is disappear. But PM error is still exist. How can I fix this error?
 

I think it would be useful to leave only PM layer visible and have a look at the error again.
Are you getting the same error if you run DRC on seal ring only (ignore other DRCs)? My guess would be that maybe your cells in the sealring are overlapping and that is causing the error.
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I think I understand what is the root cause of the problem.
Polyimide is used as a final passivation layer (insulator). Polyimide layer (PM) defines polyimide opening areas (for example, for pads, which shouldn't be covered with insulator, of course). In your layout you have PM openings on pads and on a sealring. Since you attached them to each other, they are forming effectively a wider shape (Sealring PM width = X, Pad PM width = Y, the total PM width is X +Y ) and not passing the rules for the PM width. You need to make a bigger spacing between your pads and sealring to fix this. (make only PM layer visible and you will understand how far it should go).
 
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Thx for your answer. I just simulated only sealring (not include PAD) with "wire bond DRC", But PM.W.1 error also happens again at only sealring. DRC error says >30 um for PM (except sealring region).. What can i do?

 

Did you try moving your seal ring away from the pads? If they are attached to each other, I think that Calibre cannot distinguish Seal ring from your internal circuit.
 

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