kovibb
Member level 1
- Joined
- Feb 3, 2012
- Messages
- 39
- Helped
- 2
- Reputation
- 4
- Reaction score
- 2
- Trophy points
- 1,288
- Activity points
- 1,540
Hi all,
I have a little problem in layout with nch_lvt standard cell. This cell have PDKREC/wellbody Pin layer which defined transistors´s bulk (B) pin. I used Connectivity-Driven capability of Virtuoso design kit to create layout. However I can´t connect this bulk (B) to VSS! net on Metal 1. I setup "tsmcN90rf.tf" technology file and Coinstrain group to "foundary". I tried to exploit M1_SUBv via but it doesn´t work. Annotation Browser still indicate "OPEN on NET" status. :bang:
Please how can I connect bulk of nmos (TSMC 90nm) to VSS! located on Metal 1 layer?
Thanks a lot for any reply and suggestion.
Best
Martin
I have a little problem in layout with nch_lvt standard cell. This cell have PDKREC/wellbody Pin layer which defined transistors´s bulk (B) pin. I used Connectivity-Driven capability of Virtuoso design kit to create layout. However I can´t connect this bulk (B) to VSS! net on Metal 1. I setup "tsmcN90rf.tf" technology file and Coinstrain group to "foundary". I tried to exploit M1_SUBv via but it doesn´t work. Annotation Browser still indicate "OPEN on NET" status. :bang:
Please how can I connect bulk of nmos (TSMC 90nm) to VSS! located on Metal 1 layer?
Thanks a lot for any reply and suggestion.
Best
Martin