gezzas525
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I’m currently using the TSMC 90nm LPHP technology library to synthesize designs, the process is as follows:
VHDL CodeRTL CompilerSynthesized VerilogEncounterGDSII Stream
I want to then be able to pull the design into virtuoso for simulation however I’ve tried various ways and can’t get the .GDS to read in correctly, the issue could be the TSMC library that I’m using or the version of Virtuoso. I do have the backend and frontend of the design kit.
Also I’m assuming I need model files for the transistors when doing spice simulations? I noticed these are not in my design kit.
I will put the error messages on here tonight but if anyone has the correct procedure then it will be a great help.
Kleo
VHDL CodeRTL CompilerSynthesized VerilogEncounterGDSII Stream
I want to then be able to pull the design into virtuoso for simulation however I’ve tried various ways and can’t get the .GDS to read in correctly, the issue could be the TSMC library that I’m using or the version of Virtuoso. I do have the backend and frontend of the design kit.
Also I’m assuming I need model files for the transistors when doing spice simulations? I noticed these are not in my design kit.
I will put the error messages on here tonight but if anyone has the correct procedure then it will be a great help.
Kleo