TSMC 0.18um Breakdown voltage

[OZZAA]

I want to design a power amplifier (PA) while using TSMC 0.18um.
I used the CMOS which has VDD=1.8 volts.
the questions are
can I set the VDD=VDS(Q)= 1.8 V without any proplem?
the instantanous voltage across the trasistor is 2VDD ( VDS(Q)+the amplitude of the signal in case of using RFC inductor.
is it right or i have to make the VDS(Q)= only 0.9V

 

[Dominik Przyborowski]

Read process documentation. There is an answer for your question.

And be mercy ul for us.
You even didn't mentioned what kind of transistors you are using.
Also, what kind of breakdown you have on mind?
There are different numbers for different parts of transistor.

 

[Ata_sa16]

I want to design a power amplifier (PA) while using TSMC 0.18um.
I used the CMOS which has VDD=1.8 volts.
the questions are
can I set the VDD=VDS(Q)= 1.8 V without any proplem?
the instantanous voltage across the trasistor is 2VDD ( VDS(Q)+the amplitude of the signal in case of using RFC inductor.
is it right or i have to make the VDS(Q)= only 0.9V

It is 3.3 volts.

Dont make mistake I am not taking about DC level, you need to consider swing.

Lest say Vg drops to vth (for class A) and vth=0.5 and VD goes to 2*VDD so

Imagine VDD=1.8 and then VDG = 2*1.8 - 0.5 = 3.1 this is safe

but VDD=2 and VDG = 3.5 might not be safe (still safe but you may have reliability issues)

same thing for VDS and VGS

 

[OZZAA]

And be mercy ul for us.
You even didn't mentioned what kind of transistors you are using.
Also, what kind of breakdown you have on mind?
There are different numbers for different parts of transistor.

This is the type of used transistor

I meant the breakdown that will happen from increasing the VDS to higher than 1.8 V, (BVds).

It is 3.3 volts.

Dont make mistake I am not taking about DC level, you need to consider swing.

Sorry, I do not understand your comment very well.

Lest say Vg drops to vth (for class A) and vth=0.5 and VD goes to 2*VDD so

Imagine VDD=1.8 and then VDG = 2*1.8 - 0.5 = 3.1 this is safe

but VDD=2 and VDG = 3.5 might not be safe (still safe but you may have reliability issues)

same thing for VDS and VGS

do you mean Class B or Class A.
if the Vgs is equals to the Vth this is class B not Class A, is it right?

 

[Dominik Przyborowski]

There are various breakdown mechanism and we can distinguish:
1. Hard breakdown (permanent damage)
2. Soft breakdown
Also, transistor is complicated device so, various types of breakdown can occurs:
A. Gate Insulator breakdown
B. Junction breakdown
C. Channel breakdown

Soft breakdown is like lightning, due to high electric field acting on gate Insulator, charge start to leak through the Insulator defects and finały create a way to channel. We see it as increased leakage current in gate with glitch, after which current back to "standard" value.

The numbers can be different for all above types.
Usually junctions can resist 6-10 V, gate dielectric has strength in order of 0.5V/nm (so if you gate thickness is 5nm it can resist up to 2.5V).
High electric field in Channel (Vds/L) generates Towsend ionisation in Channel and burns transistor. This number depends on channel length, and might be in order of tens or even hundred V/um.

The other question is what voltage/electric field is safe for transistor to ensure high yield and reliable work for long time.
Typical limits considered by foundries is nominal VDD+10%. It means that 2.08V is max value of Vgs and Vgd for which you fet is ensured to work fine.
For Vds the value is length dependant and usually for Vdb and Vsb, numbers are much higher than supply (it is a pn junction so is quite reliable).

If you want be safe, follow 1.1*VDD rule and check SOA during transient.

 

[Ata_sa16]

I wrote Vg DROPS to vth. In class A minimum Vg is Vth.

I explained it very clear with numbers. you need to check swing that is it.

VDG = VD - VG < 3.3 (not dc values, signal swing)

better say VDG(max swing) = VD(max) - VG(min) < 3.3


I did some tapeouts with 180nm so these numbers are real.

 

[OZZAA]

If you want be safe, follow 1.1*VDD rule and check SOA during transient.

Thank you so much for the detailed answer.

I wrote Vg DROPS to vth. In class A minimum Vg is Vth.

I explained it very clear with numbers. you need to check swing that is it.

VDG = VD - VG < 3.3 (not dc values, signal swing)

better say VDG(max swing) = VD(max) - VG(min) < 3.3


I did some tapeouts with 180nm so these numbers are real.

I catch your answer now, thank you so much.
Also, what is meant by the 1.8 V in the transistor attached in the above?

 

[Ata_sa16]

They are 2 different devices. For PA you need to use 3.3 volts.

we have both 1.8 and 3.3 volt transistors, one for low and another one for high voltages.

With 1.8 you cannot get a good output power.

 

[OZZAA]

,

They are 2 different devices. For PA you need to use 3.3 volts.

we have both 1.8 and 3.3 volt transistors, one for low and another one for high voltages.

With 1.8 you cannot get a good output power.

I have to use the 1.8 V because it has the lowest channel length 0.18 um ... for high frequency applications beyond 20 GHz
I ask about the value of 1.8 V.
this value is the maximum value of the VDS ?? if not what is the meaning of 1.8 V??
Also, If I used the 1.8 transistor and the VDD = 1.8
if the maximum instantenous draing voltage (the dc level (1.8) and the maximum swing (1.8 amplitude)) will be 2*VDD=2*1.8=3.6, it would make a problem ??