TSMC 0.18 Layout Pitch + some general considerations/questions

[Michele.A]

Hi everybody,

I'm dealing with a TSMC 0.18 design, which I am new to and there is something I am quite puzzled about, although other designers take it for granted...
So here' s the thing: I call layout pitch the minimum delta between two layout dimensions. For instance, if you can have a channel length of 180nm and the next one is 190nm, it means that the minimum pitch of the node is 10nm. Now, here are some facts:

• The property form accepts a transistor of 185nm length, if I write 181 it gets rounded to 180, if I write 183 it becomes 185. So the minimum pitch should be 5nm

• The same is true for a poly resistor (length value rounded within 5nm)

• Layout grid is 5nm as well

So there is probably plenty enough to say YES! That's your pitch! However even if that is true, my feeling about it is that something is missing from the picture. I mean: what control does the foundry have over these 5nm?
Let's make up an example to clarify my point:

• I have a poly resistor whose sheet resistance is, say, 350Ω/square

• I make a resistor 1um wide, so I need 2um to have a 700Ω resistor

• Now following the pitch, or just putting numbers in the pcell form, I could make a resistor 2.005um long, that is 701.75Ω, that is I have a 0.25 °/oo granularity! And this of course just because I have two squares, if I had more I could layout super-duper resistors with ultra odd values...

And this is where I just can't believe that :!:

I can't believe that because I don't think you can achieve such a tight control on the litography process. But, on the other hand, I haven't been able to find the proper parameters in the PDK documentation. The resistors do have a δW and δL in their model, but that is a fixed value and I couldn't find a statistical model for those. On the other hand, transistors do have XL and XW parameters, used to calculate effective channel length and width, which have a Gaussian distribution associated. Not sure if I can use those data, though.

Any suggestions, thoughts, hints?

Michele

 

[erikl]

Any suggestions, thoughts, hints?

Process variation of (resistor) values is in the order of ±30%, PVT variation easily may reach -50/+100%. You can never rely on absolute values of IC resistors. Analog designs always should depend on differential accuracy of symmetrical (common centroid layout) devices. If you need absolute accuracy, rely on appropriate bandgap voltages -- not on currents resp. resistors -- or use an accurate external resistor, or individual trimming + regulation.

 

[Michele.A]

Hi Erikl,

probably I didn't make my point clear enough. What you say is without the slightest doubt what I am used to bare in mind when designing.
Here I find myself, however, with an already made design using odd resistor values. Besides considerations of PVT variations, which is the main point of course, I am trying to make another point, which is:

=======> even if you had no PVT variations, how could you think you can control the process down to a precision of - say - 5nm over 5um?!? <====

So I am trying to make this point clear. In order to do that, I need to find or estimate the accuracy with which TSMC (or any other for that matter, as I suspect this to be a pretty general concept) can control the length of a resistor.

Again, my question is this:

can the tech provide you with a resistor 5um long, and another 5.005um long? Can they really do that? With which spread?

Thanks,

Michele

 

[erikl]

can the tech provide you with a resistor 5um long, and another 5.005um long? Can they really do that?

Hi Michele,

surely not with absolute precision. But if these 2 resistors are arranged as close as possible, the second one will be about 1%o longer than the first one.

With which spread?

You better try and ask your foundry! :razz:

Best regards, erikl

 

[Michele.A]

Hi Michele,

surely not with absolute precision. But if these 2 resistors are arranged as close as possible, the second one will be about 1%o longer than the first one.

Hi Erikl,

this is exactly what I cannot believe. It may be true, but intuitively I don't expect their accuracy to be that high. In other terms, I expect such a process to provide me a resistor having a L = Lo ± Δ(L) and this Δ(L) being a statistical value whose σ is larger than 5nm for Lo = 5µm.
So while it's true that the first resistor will be about 1%o longer, it is also true that this "about-ness" is greater than 1%o, which makes the "about" part much more relevant than the other.
Moreover, I am now taking a 5µm resistor, what about a 10µm one? Again 1%o longer than the first one?

You better try and ask your foundry! :razz:

Best regards, erikl

Oh yes, already started the "procedure"

M

p.s. thank you!